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Highpoint SCSI & RAID Devices Driver

Controller Register Map¶

  1. Highpoint Scsi & Raid Devices Driver Win 7
  2. Highpoint Scsi & Raid Devices Drivers
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  4. Highpoint Scsi & Raid Devices Driver Updater
  5. Highpoint SCSI & RAID Devices Driver

Highpoint Scsi & Raid Devices Driver Win 7

For RR44xx Intel IOP based adapters, the controller IOP is accessed via PCI BAR0 and BAR2

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BAR0 offsetRegister
0x11C5CLink Interface IRQ Set
0x11C60Link Interface IRQ Clear
BAR2 offsetRegister
0x10Inbound Message Register 0
0x14Inbound Message Register 1
0x18Outbound Message Register 0
0x1COutbound Message Register 1
0x20Inbound Doorbell Register
0x24Inbound Interrupt Status Register
0x28Inbound Interrupt Mask Register
0x30Outbound Interrupt Status Register
0x34Outbound Interrupt Mask Register
0x40Inbound Queue Port
0x44Outbound Queue Port

For Intel IOP based adapters, the controller IOP is accessed via PCI BAR0:

BAR0 offsetRegister
0x10Inbound Message Register 0
0x14Inbound Message Register 1
0x18Outbound Message Register 0
0x1COutbound Message Register 1
0x20Inbound Doorbell Register
0x24Inbound Interrupt Status Register
0x28Inbound Interrupt Mask Register
0x30Outbound Interrupt Status Register
0x34Outbound Interrupt Mask Register
0x40Inbound Queue Port
0x44Outbound Queue Port

For Marvell not Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:

BAR0 offsetRegister
0x20400Inbound Doorbell Register
0x20404Inbound Interrupt Mask Register
0x20408Outbound Doorbell Register
0x2040COutbound Interrupt Mask Register
BAR1 offsetRegister
0x0Inbound Queue Head Pointer
0x4Inbound Queue Tail Pointer
0x8Outbound Queue Head Pointer
0xCOutbound Queue Tail Pointer
0x10Inbound Message Register
0x14Outbound Message Register
0x40-0x1040Inbound Queue
0x1040-0x2040Outbound Queue

Highpoint Scsi & Raid Devices Drivers

For Marvell Frey IOP based adapters, the IOP is accessed via PCI BAR0 and BAR1:

BAR0 offsetRegister
0x0IOP configuration information.
BAR1 offsetRegister
0x4000Inbound List Base Address Low
0x4004Inbound List Base Address High
0x4018Inbound List Write Pointer
0x402CInbound List Configuration and Control
0x4050Outbound List Base Address Low
0x4054Outbound List Base Address High
0x4058Outbound List Copy Pointer Shadow Base Address Low
0x405COutbound List Copy Pointer Shadow Base Address High
0x4088Outbound List Interrupt Cause
0x408COutbound List Interrupt Enable
0x1020CPCIe Function 0 Interrupt Enable
0x10400PCIe Function 0 to CPU Message A
0x10420CPU to PCIe Function 0 Message A
0x10480CPU to PCIe Function 0 Doorbell
0x10484CPU to PCIe Function 0 Doorbell Enable

I/O Request Workflow of Not Marvell Frey¶

All queued requests are handled via inbound/outbound queue port.A request packet can be allocated in either IOP or host memory.

To send a request to the controller:

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  • Get a free request packet by reading the inbound queue port orallocate a free request in host DMA coherent memory.

    The value returned from the inbound queue port is an offsetrelative to the IOP BAR0.

    Requests allocated in host memory must be aligned on 32-bytes boundary.

  • Fill the packet.

  • Post the packet to IOP by writing it to inbound queue. For requestsallocated in IOP memory, write the offset to inbound queue port. Forrequests allocated in host memory, write (0x80000000 (bus_addr>>5))to the inbound queue port.

  • The IOP process the request. When the request is completed, itwill be put into outbound queue. An outbound interrupt will begenerated.

    For requests allocated in IOP memory, the request offset is posted tooutbound queue.

    For requests allocated in host memory, (0x80000000 (bus_addr>>5))is posted to the outbound queue. If IOP_REQUEST_FLAG_OUTPUT_CONTEXTflag is set in the request, the low 32-bit context value will beposted instead.

  • The host read the outbound queue and complete the request.

    For requests allocated in IOP memory, the host driver free the requestby writing it to the outbound queue.

Non-queued requests (reset/flush etc) can be sent via inbound messageregister 0. An outbound message with the same value indicates the completionof an inbound message.

I/O Request Workflow of Marvell Frey¶

All queued requests are handled via inbound/outbound list.

To send a request to the controller:

  • Allocate a free request in host DMA coherent memory.

    Requests allocated in host memory must be aligned on 32-bytes boundary.

  • Fill the request with index of the request in the flag.

    Fill a free inbound list unit with the physical address and the size ofthe request.

    Set up the inbound list write pointer with the index of previous unit,round to 0 if the index reaches the supported count of requests.

  • Post the inbound list writer pointer to IOP.

  • The IOP process the request. When the request is completed, the flag ofthe request with or-ed IOPMU_QUEUE_MASK_HOST_BITS will be put into afree outbound list unit and the index of the outbound list unit will beput into the copy pointer shadow register. An outbound interrupt will begenerated.

  • The host read the outbound list copy pointer shadow register and comparewith previous saved read pointer N. If they are different, the host willread the (N+1)th outbound list unit.

    The host get the index of the request from the (N+1)th outbound listunit and complete the request.

Non-queued requests (reset communication/reset/flush etc) can be sent via PCIeFunction 0 to CPU Message A register. The CPU to PCIe Function 0 Message registerwith the same value indicates the completion of message.

Highpoint Scsi & Raid Devices Driver Updater

User-level Interface¶

The driver exposes following sysfs attributes:

NAMER/WDescription
driver-versionRdriver version string
firmware-versionRfirmware version string

Highpoint SCSI & RAID Devices Driver

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Highpoint SCSI & RAID Devices Driver

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